The present disclosure relates to integrated circuit (IC) structures, and more specifically, to an IC structure having stacked active devices including through silicon vias (TSVs) having a metal resistant to high temperatures and a method of forming same.
Integrated circuit structures continue to scale to smaller sizes with increased circuit density within each chip. One approach to continue to decrease chip package size, e.g., from 22 nanometers to 14 nanometers and beyond, employs monolithic three dimensional (3D) structures. Monolithic 3D structures use stacked chips and/or increasing numbers of successive semiconductor layers. In formation of the transistor and other active devices on the various semiconductor layers in monolithic 3D structures, anneals are performed to activate the devices, e.g., to diffuse dopants on the semiconductor layers. As the IC structures are formed, back-end-of-line (BEOL) and far BEOL (FBEOL) copper interconnects are formed over the active devices to scale the wiring. One limitation to continued use of monolithic 3D structures is that the anneals necessary to activate active devices in the various semiconductor layers ideally use temperatures above 400° C., which can also damage previously formed BEOL and FBEOL interconnect structures. Approaches to address this challenge employ laser annealing to activate active devices in the semiconductor layers, and shield layers to protect other interconnect layers. The use of the shield layers increases costs and process time.